The present invention relates to metal oxide semiconductor (MOS), silicon-on-insulator (SOI) and metal-nitride-oxide semiconductor (MNOS/SNOS) technologies, and to memory cells and arrays which incorporate two bits of information per cell. In particular, the invention involves both vertically integrated (stacked) structures and shared active region structures which combine fixed threshold transistors and alterable threshold, non-volatile (NV) memory transistors into a two bit/cell structure in which selection from the two bits is made by writing or erasing the NV memory transistor. This approach has application, for example, to memory arrays such as ROM arrays, where it permits a single ROM array to function electrically as two separate arrays. The arrays are selected by a write/erase operation.
Two of the critical continuing needs of the microelectronics industry are to increase device packing densities and to enhance performance characteristics such as the speed of operation. The ongoing attempts to scale device sizes and associated structures has been successful to date in reducing the size and increasing the density of monolithic integrated circuits, albeit with some problems such as short channel effects.
Recently, another approach has emerged for increasing device density in the form of MOS vertical integration using devices which are stacked one above the other. This approach has significant potential for increased device packing density. In addition, in CMOS technology, the stacked structure eliminates isolation wells, decreases latchup, and provides decreased wire routing complexity. An example of a stacked CMOS inverter configuration is described in Colinge et al., Stacked Transistors CMOS (ST-MOS), an NMOS Technoloqy Modified to CMOS, IEEE Transactions on Electron Devices, Vol. ED-29, pp. 585-589 (1982). Referring to FIG. 1, the Colinge et al. structure starts with a conventional NMOS structure formed in a silicon substrate 10, uses the NMOS gate 11 for both transistors, and adds a selectively implanted, laser-recrystallized polycrystalline silicon layer 12 which forms the PMOS source/drain (S/D) regions 13 and 15 together with intermediate channel region 14. The PMOS S/D 15 is formed in contact with NMOS S/D 16 to provide electrical interconnection for the stacked inverter.
Another stacked CMOS structure which also uses a single common gate and recrystallized polysilicon for the PMOS source/channel/drain is described in Chen et al., Stacked CMOS SRAM Cell, IEEE Electron Device Letters, Vol. 4, p. 272 (1983).
Still another stacked CMOS configuration is described in Kawamura et al., Three-Dimensional CMOS IC's Fabricated By Using Beam Recrystallization, IEEE Electron Device Letters, Vol. 4, p. 366 (1983). This approach forms two "upright" NMOS and PMOS transistors using separate gates as well as separate source/drain diffusions. The lower NMOS device is formed using standard silicon technology, then a composite phosphosilicate glass (PSG)-nitride composite insulation is formed over the PMOS device. The NMOS transistor is then formed over the PMOS transistor by depositing a second layer of polysilicon which is recrystallized and selectively doped to form the NMOS source/channel/drain, then depositing and forming a third layer of poly onto the NMOS gate.
Combined vertical and horizontal integration is described in Gibbons et al, Stacked MOSFETs in a Single Film of Laser-Recrystallized Polysilicon, IEEE Electron Device Letters, Vol. 3, p. 191 (1982). Here, two transistors are provided in a cross-shaped single gate configuration. The paired opposite ends of the cross form the source/drain of the two transistors. The gates are located at the crossing of the two transistor channels, where the upper and lower surfaces of the polysilicon layer serve as the gates for the two transistors.
In short, the above techniques apply polysilicon recrystallization to increase the density and/or enhance operation characteristics of MOS/CMOS transistors.
The only stacked, nonvolatile, alterable threshold structure of which I am aware is described in my commonly assigned U.S. Pat. No. 4,619,034. That application utilizes laser recrystallization of polysilicon to permit the formation of an inverted memory transistor which comprises from top to bottom, channel-oxide-nitride-silicon gate electrode-insulator. The nitride is formed before the oxide, which permits forming the oxide by conversion of the nitride. The conversion process provides exceptional quality and precise, controllable reproducible growth rates for the very thin (approximately 20 Angstroms thick) memory silicon oxide.
My above co-pending application discloses, but does not specifically depict, a common gate, vertically stacked nonvolatile memory device pair. The actual construction of such a device is shown in FIG. 2. The device comprises a piggyback configuration of a standard SNOS trigate NVAT memory structure 20 and an overlying stacked SOI NVAT memory gate structure 25. The trigate structure is formed conventionally on silicon substrate 21 using source/drain diffusions 22, polysilicon gate 23 and a composite memory gate dielectric 24. The dielectric includes a layer of oxide 24OX which is formed to the three-section, trigate source- and drain-protected configuration (which is described in commonly assigned Naber et al., U.S. Pat. No. 3,719,866) and an overlying charge-storage silicon nitride layer 24NI. The disclosed SOI transistor 25 also has a trigate configuration. The device 25 is configured with the common polysilicon gate 23, overlying nitride 26NI, and the trigate oxide 260X. A recrystallized selectively doped second polysilicon layer forms the source and drain 27 and the channel 28 for the SOI memory device 25. Layer 29 is an insulator such as silicon dioxide. As mentioned previously, a key aspect of the SOI structure 25 is the ability to form the memory gate oxide, here designated 26M, by conversion of the upper surface of the nitride 26NI. In addition, the stacked piggyback device configuration provides the potential for increased device density without the need for separate gates (and the attendant separate on/off and separate write/erase operations).
In view of the above discussion, it is one object of the present invention to extend the above-described, three-dimensional stacked SOI and MNOS structural approach to a plural bit, bit-selectable memory structure which uses an Erase/Write sequence to select the bit which is to be read. It is a corollary object of the present invention to extend the plural bit, bit selectable concept to memory arrays, such as read only memories (ROMs), for example, to a bank-selectable two ROM memory array which is incorporated in the physical space of a single ROM array.